1. Field of the Invention
The present invention relates to a technology for relaying data between a plurality of adapters and a controller.
2. Description of the Related Art
In recent years, improved processing ability of computers has resulted in ever increasing volume of data used by the computers. Technologies related to storage of considerable volume of data are being examined. Specifically, for example, one of the technologies called Redundant Array of Independent Disks (RAID) involves combining a plurality of hard disk drives to realize a speedy, highly reliable, and high capacity disk system.
In a disk system such as RAID, a disk array device, which includes a plurality of disks for storing data, receives commands from a host computer and performs data read and data write operation. In this process, the data that is exchanged between the host computer and the disks is cached in a cache memory of the disk array device. Generally, subsequent processes become speedy when the data is read from the cache memory instead of reading the data from the host computer or the disks.
For example, Japanese Patent No. 2567922 discloses a conventional technology in which a plurality of channels is arranged in between a host computer and a disk array device for efficient transfer of data. A plurality of channel adapters in the disk array device is connected to the host computer. In the conventional technology, a plurality of data transfer routes is formed, which includes the respective channel adapters, between a cache memory of the disk array device and the host computer.
When, for example, a command or user data from a host computer to be written onto a disk in a disk array device is input into a channel adapter, the command or the user data are transferred to a cache memory through a switch, which transforms data transfer routes into one transfer route to relay the command or the user data. The command or the user data are not directly transferred from the switch to the cache memory. In other words, the command or the user data are first transferred from the switch to a cache controller that controls the cache memory. The cache controller processes the command or the user data and then transfers the command or the user data to the cache memory. That is, for example, when the host computer issues a command to read user data, the channel adapter sends a read request to the cache controller through the switch. As a result, a processor, such as a central processing unit (CPU), in the cache controller reads the user data from the cache memory. Subsequently, the cache controller sends the user data to the channel adapter in response to the read request, and the channel adapter sends the user to the host computer.
However, because the cache controller various processes, such as processing of the read request and transferring of data between a disk and the cache memory, sometimes there is a lot of load on the cache controller. If the cache controller is busy, a delay may occur in sending a response to the read request from the cache controller to the channel adapter. If the delay is longer than a predetermined period, it causes a time-out error in the channel adapter, and the channel adapter notifies an error to the host computer.
Specifically, for example, as shown in FIG. 10, a read request is sent from a channel adapter based on a command from a host computer (not shown) to a cache controller via a switch (step S1). If processing load on a CPU in the cache controller is relatively light, user data is read from a cache memory at the earliest and is returned to the channel adapter as a read response. However, if the processing load on the CPU in the cache controller is relatively heavy, longer time is required for reading used data, which results in delay. If a predetermined period of time T elapses from the time point at which the read request was sent, a time-out error occurs in the channel adapter (step S2).
When the time-out error occurs, the channel adapter notifies the host computer and the cache controller regarding the error simultaneously (step S3). The cache controller is notified regarding the error as a hardware interrupt. Subsequently, the processor in the cache controller starts a process of reliability, availability, serviceability (RAS) for recovery, on a priority basis (step S4). This results in increasing the load on the CPU in the cache controller. When the load on the processor increases, a process of data transfer in the cache memory, which is the original function of the cache controller, is stagnated.
After completion of the RAS process, it may happen that the user data is sent from the cache controller to the channel adapter (step S5). Because the channel adapter receives the user data after the occurrence of the time-out error, i.e., when the channel adapter is not expecting any data from the cache controller, it generates an unexpected response error in the channel adapter (step S6).
Even when the unexpected response error occurs, the channel adapter notifies occurrence of the error to the cache controller as a hardware interrupt (step S7). This further increases the load on the CPU in the cache controller and affects the process of data transfer.